Starts with toggling the PS LEDs for a configurable period. The system has a bare-metal application on RPU, which Processorīefore you configure the software, first look at the applicationĭesign scheme. Linux also requires the Linux BSP to be reconfigured in sync with the new hardware platform file (XSA). For this reason, you will need to generate a new bare-metal BSP in the Vitis IDE using the hardware files generated for this design. The software for this design example requires additional drivers for components added in the PL. Most of the software blocks will remain the same as mentioned in Build Software for PS Subsystems. This use case has a bare-metal application running on an R5 core and a Linux application running on an APU Linux target. The hardware platform XSA file is generated in the specified path. Review the summary and click Finish to close the window. The Export Hardware Platform window opens. After it finishes, a Bitstream Generation Completed message will pop up. Wait for Vivado to complete implementation. Review the Launch Runs dialogue, set the proper number of jobs to run simultaneously, and click OK. OK to launch synthesis and implementation?”. Vivado displays a popup message saying “There are no implementation results available. Run synthesis, implementation, and bitstream generation: Because this design is saved from the introduction design, we have already done it. Here you can see the output products that you just generated, as shown in the following figure. In the Block Diagram Sources window, click the IP Sources tab. When the Generate Output Products process completes, click OK. There are no errors or critical warnings in this design.” If it reports any errors or critical warnings, review the previous steps and correct the errors.Ĭlick Generate Block Design in the Flow Navigator panel. A message dialog box pops up and states “Validation successful. Bitstream is only required for debugging PL designs.Ĭlick the Validate Design button on the block diagram toolbar. Note that the Vitis IDE also accepts pre-synthesis XSAs for application development. It can make the software tests and boot image generation steps easier in the Vitis IDE. The Vivado generated bitstream will be included in the XSA file. We will run implementation of the Vivado design and export the post-implementation design. Select led_8bits from the Board Interface drop-down list on the GPIO row.Įxporting the Post-Implementation Hardware Platform ¶ Select Push button 5bits from the Board Interface drop-down list on the GPIO row.ĭouble-click axi_gpio_1 to open its configurations. Search for “AXI GPIO” and double-click the AXI GPIO IP to add it to the design.ĭouble-click axi_gpio_0 to open its configurations. Right-click in the block diagram and select Add IP. The IP Details information displays, as shown in the following figure.ĭouble-click the AXI Timer IP to add it to the design.ĭouble-click the AXI Timer IP block to configure the IP, as Right-click in the block diagram and select Add IP from the IP catalog.
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